This invention generally relates to electronic systems and in particular it relates to low dropout voltage regulators with variable bandwidth based on load current.
A prior art general architecture of an internal compensated low dropout voltage regulator (LDO) is shown in FIG. 1. This LDO includes an error amplifier A1, a wide band gain stage A2 for better pole-splitting, a buffer BUF for impedance translation, an internal compensation cap Cc, a feedback resistor string R1 and R2, and an output power PMOS transistor PSW (power switch). The LDO also includes reference voltage VREF; bias voltage VBIAS; source voltage VDD; feedback voltage VFB; output current Iout; output voltage VOUT; equivalent series resistor (ESR) R_ESR; output filter capacitor C_FILT; and external load LOAD. If designed properly, the bandwidth, pole position of this LDO can be calculated by simply applying two stage amplifier equations a shown in the equations below.                               Dominant          ⁢                      xe2x80x83                    ⁢          pole          ⁢                      :                    ⁢                      xe2x80x83                    ⁢                      f            Pd                          =                  1                      2            ⁢                          π              ·                              (                                  1                  +                                      A2                    ·                                          G                      mPSW                                        ·                                          r                      oPSW                                                                      )                            ·                              r                oA1                            ·                              C                c                                                                        (        1        )                                          Second          ⁢                      xe2x80x83                    ⁢          pole          ⁢                      :                    ⁢                      xe2x80x83                    ⁢                      f            P2                          =                              A2            ·                          G              mPSW                                            2            ⁢                          π              ·                              C                FILT                                                                        (        2        )                                          Open          ⁢                      xe2x80x83                    ⁢          loop          ⁢                      xe2x80x83                    ⁢          unity          ⁢                      xe2x80x83                    ⁢          gain          ⁢                      xe2x80x83                    ⁢          bandwidth          ⁢                      :                    ⁢                      xe2x80x83                    ⁢                      f            UGBol                          =                                            g              mA1                                      2              ⁢                              π                ·                                  C                  C                                                              ·                                    R              2                                                      R                1                            +                              R                2                                                                        (        3        )            
where GmPSW is the transconductance of transistor PSW; A2 is the gain of amplifier A2; Cc is the capacitance of capacitor Cc; roA1 is the output impedance of amplifier A1; roPSW is the output impedance of transistor PSW; CFILT is the capacitance of capacitor C_FILT; and gmA1 is the transconductance amplifier A1.
To satisfy stability criteria, the second pole fP2 needs to be pushed close to or beyond the unity gain bandwidth fUGBol. As we can see from equation (2), the second pole fP2 moves with the transconductance of the power PMOS PSW, gmPSW, which is proportional to {square root over (IOUT)}. For an LDO, the output current ranges from a few uA""s to hundreds of mA""s, thus the transconductance gmPSW changes 2-3 decades and so does the second pole fP2. For a conventionally designed LDO, the bandwidth fuGBol is limited by the worst-case second pole fP2 where output current IOUT is minimum.
A low dropout voltage regulator includes: a first amplifier having a reference voltage node coupled to a first input; a second amplifier having an input coupled to an output of the first amplifier; a variable bias current source coupled to the first amplifier and having a control node coupled to an output of the second amplifier; a power switch having a control node coupled to the output of the second amplifier and having a first end coupled to a source voltage node; and a feedback circuit having an input coupled to a second end of the power switch and an output coupled to a second input of the first amplifier. The best node in the system that detects the load current level is the output of the second amplifier. This signal is used to modulate the bias current of the first amplifier by increasing the bias current when the load current increases and vice versa, which consequently modulates the transconductance of the first amplifier. This provides a higher bandwidth LDO with better transient performance and higher power supply rejection ratio.